This invention relates to the field of computer simulation of electrical systems. Specifically, the invention relates to virtual modeling of computer systems.
Various methods of modelling and simulating computer systems and other electronic systems are well known. Computer system models have generally fallen into one of two classes: processor models, and logic models. Processor models simulate the execution of computer code and are used to debug microcode and other programs before the processor for which they are intended has actually been built. Logic models are bus level simulations that cannot execute code and are instead used to debug the hardware of a system. Prior to the actual simulation, design language source files, commonly in a Hardware Description Language ("HDL"), describing the basic components modeled and a particular configuration are provided as input to a compiler to produce an HDL object file. The HDL object file is then used as input to simulator code which then performs the simulation. Primary features common or similar in both types of modeling are the ability to step through the simulation and to allow signal/waveform values or register/memory contents to be displayed and altered. The interpretation and modification of such displayed waveform values is hampered, however, by the difficulty of associating HDL source code equations with the simulation display. Typically, HDL source code equations must either be read from physical print outs, or from an editor screen on a separate computer (or on a separate window in multitasking environments). Neither of these methods provide any link between the simulation and the source file, complicating the simulation review/modification process.